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19-0734; Rev 0; 1/07
KIT ATION EVALU BLE AVAILA
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
General Description
The MAX15014-MAX15017 combine a step-down DCDC converter and a 50mA, low-quiescent-current lowdropout (LDO) regulator. The LDO regulator is ideal for powering always-on circuitry in automotive applications. The DC-DC converter input voltage range is 4.5V to 40V for the MAX15015/MAX15016, and 7.5V to 40V for the MAX15014/MAX15017. The DC-DC converter output is adjustable from 1.26V to 32V and can deliver up to 1A of load current. These devices utilize a feed-forward voltage-mode control scheme for good noise immunity in the high-voltage switching environment and offer external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. The switching frequency is internally fixed at 135kHz and 500kHz, depending on the version chosen. Moreover, the switching frequency can be synchronized to an external clock signal through the SYNC input. Light load efficiency is improved by automatically switching to a pulse-skip mode. The soft-start time is adjustable with an external capacitor. The DC-DC converter can be disabled independent of the LDO, thus reducing the quiescent current to 47A (typ). The LDO linear regulators operate from 5V to 40V and deliver a guaranteed 50mA load current. The devices feature a preset output voltage of 5V (MAX1501_A) or 3.3V (MAX1501_B). Alternatively, the output voltage can be adjusted from 1.5V to 11V by using an external resistive divider. The LDO section also features a RESET output with adjustable timeout period. Protection features include cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. All devices are available in a space-saving, high-power (2.86W), 36-pin TQFN package and are rated for operation over the -40C to +125C automotive temperature range.
Features
o Combined DC-DC Converters and Low-QuiescentCurrent LDO Regulators o 1A DC-DC Converters Operate from 4.5V to 40V (MAX15015/MAX15016) or 7.5V to 40V (MAX15014/MAX15017) o Switching Frequency of 135kHz (MAX15014/MAX15016) or 500kHz (MAX15015/MAX15017) o 50mA LDO Regulator Operates from 5V to 40V Independent of the DC-DC Converter o 47A Quiescent Current with DC-DC Converter Off and LDO On o 6A System Shutdown Current o Frequency Synchronization Input o Shutdown/Enable Inputs o Adjustable Soft-Start Time o Active-Low Open-Drain RESET Output with Programmable Timeout Delay o Thermal Shutdown and Output Short-Circuit Protection o Space-Saving (6mm x 6mm) Thermally Enhanced 36-Pin TQFN Package
MAX15014-MAX15017
Ordering Information
PART TEMP RANGE PINPACKAGE PKG CODE T3666-3 T3666-3 T3666-3 T3666-3 T3666-3 T3666-3 T3666-3 T3666-3
MAX15014AATX+ -40C to +125C 36 TQFN-EP* MAX15014BATX+ MAX15015BATX+ MAX15016BATX+ MAX15017BATX+ -40C to +125C 36 TQFN-EP* -40C to +125C 36 TQFN-EP* -40C to +125C 36 TQFN-EP* -40C to +125C 36 TQFN-EP* MAX15015AATX+ -40C to +125C 36 TQFN-EP* MAX15016AATX+ -40C to +125C 36 TQFN-EP*
Applications
Car Radios Automotive Body Control Modules Automotive Instrument Cluster Navigation Systems
MAX15017AATX+ -40C to +125C 36 TQFN-EP*
+Denotes a lead-free package. *EP = Exposed pad.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
ABSOLUTE MAXIMUM RATINGS
IN_SW, IN_LDO, DRAIN, EN_SYS, EN_SW to SGND ..............................................................-0.3V to +45V IN_LDO to IN_SW ..................................................-0.3V to +0.3V LX to SGND ...........................................-0.3V to (VIN_SW + 0.3V) LX to PGND ...........................................-0.3V to (VIN_SW + 0.3V) BST to SGND ..........................................-0.3V to (VIN_SW + 12V) BST to LX................................................................-0.3V to +12V PGND to SGND .....................................................-0.3V to +0.3V REG, DVREG, SYNC, RESET, CT to SGND............-0.3V to +12V FB, COMP_SW, SS to SGND....................-0.3V to (VREG + 0.3V) SET_LDO, LDO_OUT to SGND ..............................-0.3V to +12V C+ to PGND (MAX15015/MAX15016 only)................(VDVREG - 0.3V) to 12V C- to PGND (MAX15015/MAX15016 only) ............-0.3V to (VDVREG + 0.3V) LDO_OUT Output Current.................................Internally Limited Switch DC Current (DRAIN and LX pins combined) TJ = +125C.......................................................................1.9A TJ = +150C.....................................................................1.25A RESET Sink Current ..............................................................5mA Continuous Power Dissipation (TA = +70C) 36-Pin TQFN (derate 26.3mW/C above +70C) Single-Layer Board .....................................................2105mW 36-Pin TQFN (derate 35.7mW/C above +70C) Multilayer Board ..........................................................2857mW Operating Temperature Range .........................-40C to +125C Maximum Junction Temperature .....................................+150C Storage Temperature Range ............................-60C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER System Supply Current (Not Switching) SYMBOL CONDITIONS VFB = 1.3V, MAX15014/MAX15017 ISYS No load VFB = 1.3V, MAX15015/MAX15016 VFB = 0V, MAX15014/MAX15017 Switching System Supply Current ISW No load VFB = 0V, MAX15015/MAX15016 VEN_SYS = 14V, VEN_SW = 0V ILDO_OUT = 100A ILDO_OUT = 50mA 8.6 47 130 6 2.4 0.8 220 IEN_SYS VEN_SYS = 2.4V VEN_SYS = 14V MAX15014/MAX15017 MAX15015/MAX15016 7.5 4.5 0.5 0.6 2 2 40.0 40.0 63 200 10 A V mV A 0.85 5.6 mA 1.8 MIN TYP 0.7 MAX 1.8 mA UNITS
LDO Quiescent Current System Shutdown Current System Enable Voltage System Enable Hysteresis System Enable Input Current BUCK CONVERTER Input Voltage Range
ILDO ISHDN VEN_SYSH VEN_SYSL
A
VEN_SYS = 0V, VEN_SW = 0V EN_SYS = high, system on EN_SYS = low, system off
VIN_SW
V
2
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
ELECTRICAL CHARACTERISTICS (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS VIN_SW and IN_LDO rising, MAX15014/MAX15017 VIN_SW and IN_LDO rising, MAX15015/MAX15016 MAX15014/MAX15017 MAX15015/MAX15016 Minimum output Maximum output EN_SW = high, switching power supply is on EN_SW = low, switching power supply is off 220 IEN_SW VEN_SW = 2.4V VEN_SW = 14V MAX15014/MAX15017, VIN_SW = 9V to 40V Output Voltage VREG MAX15015/MAX15016, VIN_SW = 5.5V to 40V VIN_SW = 9.0V to 40V, MAX15014/MAX15017 VIN_SW = 5.5V to 40V, MAX15015/MAX15016 IREG = 0 to 20mA VIN_SW = 7.5V (MAX15014/MAX15017), VIN_SW = 4.5V (MAX15015/MAX15016), IREG = 20mA VSYNC = 0V, MAX15014/MAX15016 VSYNC = 0V, MAX15015/MAX15017 VSYNC = 0V, VIN_SW = 7.5V, MAX15014 (135kHz) VSYNC = 0V, VIN_SW = 4.5V, MAX15016 (135kHz) Maximum Duty Cycle DMAX VSYNC = 0V, VIN_SW = 4.5V, MAX15015 (500kHz) VSYNC = 0V, VIN_SW = 7.5V, MAX15017 (500kHz) Minimum LX Low Time SYNC High-Level Voltage SYNC Low-Level Voltage VSYNC = 0V 122 425 90 90 90 90 94 2.2 0.8 136 500 7.6 4.75 1 1 0.25 0.5 0.5 0.6 2 2 8.4 5.25 V 2.4 0.8 MIN 6.7 3.90 TYP 7.0 4.08 0.54 0.3 1.26 32 1 MAX 7.4 V 4.25 V V A V mV A UNITS
MAX15014-MAX15017
Undervoltage Lockout Threshold
UVLOTH
Undervoltage Lockout Hysteresis Output Voltage Range Output Current EN_SW Input Voltage Threshold EN_SW Hysteresis Switching Enable Input Current
UVLOHYST VOUT IOUT VEN_SWH VEN_SWL
INTERNAL VOLTAGE REGULATOR
Line Regulation Load Regulation Dropout Voltage OSCILLATOR Frequency Range fCLK
mV/V V V
150 575 98 98
kHz
% 96 98 ns V
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
ELECTRICAL CHARACTERISTICS (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYNC Frequency Range Ramp Level Shift (Valley) ERROR AMPLIFER Soft-Start Reference Voltage Soft-Start Current FB Regulation Voltage FB Input Range FB Input Current COMP Voltage Range Open-Loop Gain Unity-Gain Bandwidth PWM Modulator Gain CURRENT-LIMIT COMPARATOR Pulse Skip Threshold Cycle-by-Cycle Current Limit Number of Consecutive ILIM Events to Hiccup Hiccup Timeout POWER SWITCH Switch On-Resistance Switch Gate Charge Switch Leakage Current BST Quiescent Current BST Leakage Current CHARGE PUMP (MAX15015/MAX15016) C- Output Voltage Low C- Output Voltage High DVREG to C+ On-Resistance LX to PGND On-Resistance LDO Input Voltage Range Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis VIN_LDO UVLO_LDOTH UVLO_LDOHYST VIN_LDO rising 5 3.90 4.1 0.3 40 4.25 V V V Sinking 10mA Relative to DVREG, sourcing 10mA Sourcing 10mA Sinking 10mA 0.1 0.1 10 12 V V VBST - VLX = 6V VBST - VLX = 6V VIN_SW = VIN_LDO = VLX = VDRAIN = 40V, VFB = 0V VBST = 40V, VDRAIN = 40V, VFB = 0V, DVREG = 5V VBST = VDRAIN = VLX = VIN_SW = VIN_LDO = 40V, EN_SW = 0V 400 0.15 0.4 4 10 600 1 0.80 nC A A A IPFM IILIM 100 1.3 200 2 7 512 300 2.6 mA A -- Clock periods fSYNC = 500kHz, MAX15015/MAX15017 fSYNC = 135kHz, MAX15014/MAX15016 VSS ISS VFB VFB IFB VFB = 1.244V ICOMP = -500A to +500A VSS = 0V 1.210 7 1.210 0 -250 0.25 80 1.8 10 10 1.235 12 1.235 1.260 17 1.260 1.5 +250 4.5 V A V V nA V dB MHz V/V SYMBOL fSYNC CONDITIONS MAX15014/MAX15016 MAX15015/MAX15017 MIN 100 400 0.3 TYP MAX 200 600 UNITS kHz V
4
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
ELECTRICAL CHARACTERISTICS (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Output Current SYMBOL IOUT CONDITIONS VIN = 6V (Note 2) ILDO_OUT = 100A ILDO_OUT = 1mA 6V VIN_LDO 40V, ILDO_OUT = 1mA 1mA IOUT 50mA, VIN_LDO = 14V Output Voltage VLDO_OUT ILDO_OUT = 100A ILDO_OUT = 1mA SET_LDO = SGND, MAX1501_B 6V VIN_LDO 40V, ILDO_OUT = 1mA 1mA ILDO_OUT 50mA, VIN_LDO = 14V Adjustable Output Voltage Range VADJ VSET_LDO > 0.25V VIN_LDO = 5V, MAX1501_A VIN_LDO = 4.0V, MAX1501_B IOUT = 10mA IOUT = 50mA IOUT = 10mA IOUT = 50mA 400 1.220 (Note 3) ISET_LDO VSET_LDO = 11V IOUT = 10mA, f = 100Hz, 500mVP-P, VLDO_OUT = 5V IOUT = 10mA, f = 1MHz, 500mVP-P, VLDO_OUT = 5V Short-Circuit Current ISC 125 1.241 185 0.5 78 dB 24 185 300 mA 100 1.265 MIN 65 4.90 4.90 4.85 4.85 3.22 3.22 3.2 5 5 5 5 3.3 3.3 3.3 TYP MAX 200 5.06 5.06 5.15 5.15 3.35 3.35 3.4 V UNITS mA
MAX15014-MAX15017
SET_LDO = SGND, MAX1501_A
3.2 1.5
3.3
3.4 11.0 0.6 0.82 0.1 0.4 s V mV nA V V
Dropout Voltage
VDO
Startup Response Time SET_LDO Reference Voltage Minimum SET_LDO Threshold SET_LDO Input Leakage Current VSET_LDO
From EN_SYS high to LDO_OUT rise, RL = 500, SET_LDO = SGND
Power-Supply Rejection Ratio
PSRR
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
ELECTRICAL CHARACTERISTICS (continued)
(VIN_SW = VIN_LDO = VDRAIN = 14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER RESET OUTPUT RESET Threshold RESET Output Low Voltage RESET Output High Leakage Current RESET Output Minimum Timeout Period ENABLE to RESET Minimum Timeout Period Delay Comparator Threshold (Rising) Delay Comparator Threshold Hysteresis CT Charge Current CT Discharge Current THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Shutdown Hysteresis Temperature rising +160 20 C C VCT-TH VCTTHHYST
SYMBOL
CONDITIONS RESET goes high after rising VLDO_OUT crosses this threshold (VLDO_OUT - V RESET) / IRESET = 4k V RESET = 3.3V (For MAX15_ _ _B), V RESET = 5V (For MAX15_ _ _A) When LDO_OUT reaches RESET threshold, CT = unconnected When EN_SYS goes high, CLDO_OUT = 10F, ILDO_OUT = 50mA, VLDO_OUT = 3.3V, CT = unconnected
MIN
TYP
MAX
UNITS
V RESET VRL IRH
90
92.5
95 0.4 1
%VOUT V A s
50
650
s
1.220
1.241 100
1.265
V mV
ICT-CHQ ICT-DIS
VCT = 0V
1.5
2 18
3
A mA
Note 1: Limits at -40C are guaranteed by design and not production tested. Note 2: Maximum output current is limited by package power dissipation. Note 3: This is the minimum voltage needed at SET_LDO for the system to recognize that the user wants an adjustable LDO_OUT.
6
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Typical Operating Characteristics
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, see Figures 6 and 7, TA = +25C, unless otherwise noted.)
SYSTEM SHUTDOWN CURRENT vs. TEMPERATURE
MAX15014 toc01
SWITCHING FREQUENCY vs. TEMPERATURE
MAX15014 toc02
SWITCHING FREQUENCY vs. TEMPERATURE
MAX15015A 520 SWITCHING FREQUENCY (kHz) 510 500 490 480 470 460 450
MAX15014 toc03 MAX15014 toc06
10 SYSTEM SHUTDOWN CURRENT (A) 9 8 7 6 5 4 3 2 1 0 -50 0 50 100 TEMPERATURE (C) MAX15016
140 139 SWITCHING FREQUENCY (kHz) 138 137 136 135 134 133 132 131 130 MAX15016A
530
150
-60 -40 -20 0 20 40 60 80 100 120 140 160 TEMPERATURE (C)
-60 -40 -20 0 20 40 60 80 100 120 140 160 TEMPERATURE (C)
MAXIMUM DUTY CYCLE vs. INPUT VOLTAGE (MAX15016A)
MAX15014 toc04
MAXIMUM DUTY CYCLE vs. INPUT VOLTAGE (MAX15015A)
MAX15014 toc05
ERROR AMPLIFIER OPEN-LOOP GAIN AND PHASE vs. FREQUENCY
110 100 90 80 70 60 50 40 30 20 10 0 -10 PHASE GAIN (dB) 340 GAIN 300
100 99 MAXIMUM DUTY CYCLE (%) 98 97 96 95 94 93 92 91 90 0 5 10 15 20 25 30 INPUT VOLTAGE (V) 35
100 98 MAXIMUM DUTY CYCLE (%) 96 94 92 90 88 86 84 82 80
220 180 140 100 60 0.1 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz)
40
0
5
10
15
20
25
30
35
40
INPUT VOLTAGE (V)
OUTPUT CURRENT LIMIT vs. INPUT VOLTAGE
MAX15014 toc07
TURN-ON/-OFF WAVEFORM
MAX15014 toc08
TURN-ON/-OFF WAVEFORM
MAX15014 toc09
2.5 TA = 0C OUTPUT CURRENT LIMIT (A) 2.0 TA = +25C
ILOAD = 1A
ILOAD = 100mA
1.5 TA = +85C
0V
EN_SW 2V/div
0V
EN_SW 2V/div
1.0
TA = +135C VOUT 2V/div 0V 0V 2ms/div 2ms/div VOUT 2V/div
0.5
0 0 10 20 30 INPUT VOLTAGE (V) 40 50
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PHASE (DEGREES)
260
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, see Figures 6 and 7, TA = +25C, unless otherwise noted.)
TURN-ON/-OFF WAVEFORM INCREASING VIN
ILOAD = 1A VIN 5V/div 0V 0V
TURN-ON/-OFF WAVEFORM INCREASING VIN
ILOAD = 100mA
MAX15014 toc10
MAX15014 toc11
OUTPUT VOLTAGE vs. TEMPERATURE
3.38 VIN 5V/div 3.36 OUTPUT VOLTAGE (V) 3.34 3.32 3.30 3.28 3.26 3.24 3.22 3.20 ILOAD = 1A -40 -15 10 35 60 85 TEMPERATURE (C) 110 135 ILOAD = 0A
MAX15014 toc12
3.40
VOUT 2V/div 0V 0V
VOUT 2V/div
10ms/div
10ms/div
EFFICIENCY vs. LOAD CURRENT
MAX15014 toc13
EFFICIENCY vs. LOAD CURRENT (MAX15015A)
90 80 EFFICIENCY (%) 70 EFFICIENCY (%) 60 50 40 30 VIN = 40V VIN = 12V VIN = 24V VOUT = 3.3V VIN = 4.5V
MAX15014 toc14
EFFICIENCY vs. LOAD CURRENT (MAX15014)
90 80 70 60 50 40 30 20 10 0 VIN = 40V VIN = 24V VIN = 12V VOUT = 5V VIN = 7.5V
MAX15014 toc15
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 1
100 VIN = 7.5V
VOUT = 3.3V VIN = 4.5V
100
VIN = 7.5V
VIN = 12V VIN = 24V VIN = 40V
MAX15016A ILDO_OUT = 0A 10 100 LOAD CURRENT (mA) 1000
20 10 0 1 10 100 1000 LOAD CURRENT (mA)
1
10 100 LOAD CURRENT (mA)
1000
EFFICIENCY vs. LOAD CURRENT (MAX15017A)
MAX15014 toc16
LOAD-TRANSIENT RESPONSE
MAX15014 toc17
LOAD-TRANSIENT RESPONSE
MAX15014 toc18
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 1 10 100 LOAD CURRENT (mA) VIN = 40V VIN = 24V VIN = 12V VOUT = 5V VIN = 7.5V
VIN = 12V, IOUT = 0.25A TO 1A MAX15015A VOUT AC-COUPLED 100mV/div
VIN = 4.5V, IOUT = 0.25A TO 1A MAX15015A VOUT AC-COUPLED 100mV/div
ILOAD 500mA/div 0 0 1000 200s/div 200s/div ILOAD 500mA/div
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, see Figures 6 and 7, TA = +25C, unless otherwise noted.)
MAX15014-MAX15017
LX VOLTAGE AND INDUCTOR CURRENT
MAX15014 toc19
LX VOLTAGE AND INDUCTOR CURRENT
MAX15014 toc20
MAX150_ _ VLX 5V/div 0V 0V VLX 5V/div
0V ILOAD = 40mA 2s/div
INDUCTOR CURRENT 200mA/div ILOAD = 160mA 2s/div
INDUCTOR CURRENT 100mA/div
LX VOLTAGE AND INDUCTOR CURRENT
MAX15014 toc21
MINIMUM LX PULSE WIDTH vs. LOAD CURRENT
350 LX PULSE WIDTH (ns) VLX 5V/div 300 250 200 150 100 50 VOUT = 3.3V 0 300 400 500 600 700 800 900 1000
MAX15014 toc22
400
0V
INDUCTOR CURRENT 500mA/div ILOAD = 1A 2s/div
LOAD CURRENT (mA)
LDO QUIESCENT CURRENT vs. TEMPERATURE
MAX15014 toc23
OUTPUT VOLTAGE vs. TEMPERATURE
MAX15014 toc24
OUTPUT VOLTAGE vs. TEMPERATURE
ILOAD = 1mA 3.30 LDO OUTPUT VOLTAGE (V) 3.29 3.28 3.27 3.26 3.25 3.24 MAX15015B 3.23 -40 -15 10 35 60 85 TEMPERATURE (C) 110 135 ILOAD = 50mA ILOAD = 10mA
MAX15014 toc25
70 60 LDO QUIESCENT CURRENT (A) 50 40 30 20 10 MAX15015B 0 -50 -25 0 25 50 75 TEMPERATURE (C) 100 NO LOAD ILOAD = 100A
5.10
3.31
LDO OUTPUT VOLTAGE (V)
5.05 ILOAD = 1mA 5.00 ILOAD = 10mA 4.95 ILOAD = 50mA
4.90 MAX15015A 4.85 125 -40 -15 10 35 60 85 TEMPERATURE (C) 110 135
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, see Figures 6 and 7, TA = +25C, unless otherwise noted.)
TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS
MAX15014 toc28 MAX15014 toc27
DROPOUT VOLTAGE vs. LOAD CURRENT
MAX15014 toc26
POWER-SUPPLY REJECTION RATIO
10 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 ILDO_OUT = 1mA 0.1k 1k 10k 100k FREQUENCY (Hz) 1M 10M 0V ILDO_OUT = 50mA ILDO_OUT = 10mA
900 800 DROPOUT VOLTAGE (mV) 700 600 500 400 300 200 100 0 0 10 20 30 LOAD CURRENT (mA) 40 TA = +85C TA = +25C TA = -40C VIN = 5V, ILOAD = 0 TO 50mA MAX15015A TA = +135C
ILOAD = 50mA EN_SYS 2V/div 0V
VOUT 2V/div
50
2ms/div
TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS
MAX15014 toc29
TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS
MAX15014 toc30
RLOAD = 1k EN_SYS 2V/div 0V 0V VOUT 2V/div 0V 10ms/div 0V
MAX15015B RLOAD = 66 EN_SYS 2V/div
VLDO_OUT 1V/div
10ms/div
TURN-ON/-OFF WAVEFORM TOGGLING EN_SYS
MAX15014 toc31
TURN-ON/-OFF WAVEFORM INCREASING VIN
ILOAD = 50mA EN_SYS 2V/div
MAX15014 toc32
MAX15015B RLOAD = 660
0V 0V VLDO_OUT 1V/div 0V 0V
VIN 5V/div
VLDO_OUT 2V/div
10ms/div
10ms/div
10
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
Typical Operating Characteristics (continued)
(VIN_SW = VIN_LDO = VDRAIN =14V, VEN_SYS = VEN_SW = 2.4V, VREG = VDVREG, VSYNC = VSET_LDO = VSGND = VPGND = 0V, CREG = 1F, CIN_SW = 0.1F, CIN_LDO = 0.1F, CLDO_OUT = 10F, CDRAIN = 0.22F, see Figures 6 and 7, TA = +25C, unless otherwise noted.)
LDO TURN-ON/-OFF WAVEFORM WITH INCREASING VIN
ILOAD = 5mA
MAX15014-MAX15017
MAX15014 toc33
TURN-ON/-OFF WAVEFORM INCREASING VIN
MAX15014 toc34
MAX15015B RLOAD = 66 VIN 2V/div 0V
VIN 5V/div
0V VLDO_OUT 1V/div
VLDO_OU 2V/div 0V 10ms/div 0V
10ms/div
TURN-ON/-OFF WAVEFORM INCREASING VIN
LOAD-TRANSIENT RESPONSE
MAX15014 toc36
MAX15014 toc35
MAX15015B RLOAD = 660 VIN 5V/div 0V VLDO_OUT AC-COUPLED 100mV/div
VLDO_OUT 1V/div 0V 0
ILOAD 20mA/div
10ms/div
100s/div
INPUT-VOLTAGE STEP RESPONSE
MAX15014 toc37
RESIDUAL SWITCHING NOISE ON THE LDO OUTPUT
MAX15014 toc38
MAX15015B ILOAD = 1mA VIN 20V/div 0V VLDO_OUT AC-COUPLED 100mV/div
DC-DCLOAD = 1A
VLDO_OUT 10mV/div
1ms/div
400ns/div
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11
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Pin Description
PIN MAX15014/ MAX15017 1, 2, 3, 9, 12, 14, 16, 19, 24, 26, 27, 30, 35 23, 28 4 MAX15015/ MAX15016 1, 2, 3, 9, 12, 14, 16, 19, 24, 26, 27, 30, 35 -- 4 NAME FUNCTION
N.C. I.C. RESET
No Connection. Not internally connected. Leave unconnected or connect to SGND. Internally Connected. Leave unconnected. Active-Low Reset Output. When the rising VLDO_OUT voltage crosses the reset threshold, RESET goes high after an adjustable delay. Pull up RESET to LDO_OUT with at least 4k. RESET is an active-low open-drain output. Signal Ground Connection. Connect SGND and PGND together at one point near the input bypass capacitor negative terminal. Reset Timeout Delay Capacitor Connection. CT is pulled low during reset. When out of reset, CT is pulled up to an internal 3.6V rail with a 2A current source. When the rising CT voltage reaches the trip threshold (typically 1.24V), RESET is deasserted. When EN_SYS is low or in thermal shutdown, CT is low. Switching Regulator Enable Input (Active High). If EN_SW is high and EN_SYS is high, the switching power supply is enabled. EN_SW is internally pulled down to SGND through a 0.5A current sink. Active-High System Enable Input. Connect EN_SYS high to turn on the system. The LDO is active if EN_SYS is high; once EN_SYS is high, the switching regulator can be turned on if EN_SW is high. EN_SYS is internally pulled down to SGND through a 0.5A current sink. LDO Feedback Input/Output Voltage Setting. Connect SET_LDO to SGND to select the preset output voltage (5V or 3.3V). Connect SET_LDO to an external resistordivider network for adjustable output operation. Linear Regulator Output. Bypass with at least 10F low-ESR capacitor from LDO_OUT to SGND. In the 5V LDO versions (A), the LDO operates in dropout below 6V down to the UVLO trip point. LDO Input Voltage. The input voltage range for the LDO extends from 5V to 40V. Bypass with a 0.1F ceramic capacitor to SGND. High-Side Gate Driver Supply. Connect BST to the cathode of the bootstrap diode and to the positive terminal of the bootstrap capacitor. Source Connection of Internal High-Side Switch. Connect both LX pins to the inductor and the cathode of the freewheeling diode. Drain Connection of the Internal High-Side Switch. Connect both DRAIN inputs together. Power Ground Connection. Connect the input bypass capacitor negative terminal, the anode of the freewheeling diode, and the output filter capacitor negative terminal to PGND. Connect PGND to SGND together at a single point near the input bypass capacitor negative terminal.
5
5
SGND
6
6
CT
7
7
EN_SW
8
8
EN_SYS
10
10
SET_LDO
11
11
LDO_OUT
13 15 17, 18 20, 21
13 15 17, 18 20, 21
IN_LDO BST LX DRAIN
22
22
PGND
12
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
Pin Description
PIN MAX15014/ MAX15017 -- 25 MAX15015/ MAX15016 23 25 NAME CDVREG FUNCTION Charge-Pump Flying Capacitor Negative Connection (MAX15015/MAX15016 only) Gate Drive Supply for the High-Side MOSFET Driver. Connect to REG and to the anode of the bootstrap diode for MAX15014/MAX15017. Connect to REG for MAX15015/MAX15016. Charge-Pump Flying Capacitor Positive Connection (MAX15015/MAX15016 only). Connect to the positive terminal of the external pump capacitor and to the anode of the bootstrap diode. Oscillator Synchronization Input. SYNC can be driven by an external clock to synchronize the switching frequency. Connect SYNC to SGND when not used. Error Amplifier Output. Connect COMP to the compensation feedback network. Feedback Regulation Point. Connect to the center tap of a resistive divider from converter output to SGND to set the output voltage. The FB voltage regulates to the voltage present at SS (1.235V). Soft-Start and Reference Output. Connect a capacitor from SS to SGND to set the soft-start time. See the Applications Information section to calculate the value of the CSS capacitor. Internal Regulator Output. 5V output for the MAX15015/MAX15016 and 8V output for the MAX15014/MAX15017. Bypass to SGND with at least a 1F ceramic capacitor. Supply Input Connection. Connect to IN_LDO and an external voltage source from 4.5V to 40V. EN_SW and EN_SYS must be high and IN_SW must be above its UVLO threshold for operation of the switching regulator. Exposed Pad. The exposed pad must be electrically connected to SGND. For an effective heatsinking, solder the exposed pad to a large copper plane.
MAX15014-MAX15017
--
28
C+
29 31 32
29 31 32
SYNC COMP FB
33
33
SS
34
34
REG
36
36
IN_SW
--
--
EP
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13
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Detailed Description
The MAX15014-MAX15017 combine a voltage-mode buck converter with an internal 0.5 power MOSFET switch and a low-quiescent-current LDO regulator. The buck converter of the MAX15015/MAX15016 has a wide input voltage range of 4.5V to 40V. The MAX15014/MAX15017's input voltage range is 7.5V to 40V. Fixed switching frequencies of 135kHz and 500kHz are available. The internal low RDS_ON switch allows for up to 1A of output current, and the output voltage can be adjusted from 1.26V to 32V. External compensation and voltage feed-forward simplify loop compensation design and allow for a wide variety of L and C filter components. All devices offer an automatic switchover to pulse-skipping (PFM) mode, providing low quiescent current and high efficiency at light loads. Under no load, PFM mode operation reduces the current consumption to 5.6mA for the MAX15014/ MAX15017 and 8.6mA for the MAX15015/MAX15016. In shutdown (DC-DC and LDO regulator off), the supply current falls to 6A. Additional features include a programmable soft-start, cycle-by-cycle current limit, hiccup-mode output short-circuit protection, and thermal shutdown. The LDO linear regulator operates from 5V to 40V and delivers a guaranteed 50mA load current. The devices feature a preset output voltage of 5.0V (MAX1501_A) or 3.3V (MAX1501_B). Alternatively, the output voltage can be adjusted from 1.5V to 11V using an external resistive divider. The LDO section also features a RESET output with adjustable timeout period.
Enable Inputs and UVLO
The MAX15014-MAX15017 feature two logic inputs, EN_SW (active-high) and EN_SYS (active-high) that can be used to enable the switching power supply and the LDO_OUT outputs. When VEN_SW is higher than the threshold and EN_SYS is high, the switching power supply is enabled. When EN_SYS is high, the LDO is active. When EN_SYS is low, the entire chip is off (see Table 1).
IN_SW
EN_SYS
IN_LDO
C-
C+
DVREG
DVREG IN_LDO 7.0V OR 4.1V VINT REG REG_LDO VREF EN_SW VREG_OK + VINT + UVLO_SW TSD SHDN VINT VREF VREFOK THERMAL SHDN TSD VREFOK VINTOK 4.1V UVLO_LDO VREFOK VINTOK VREG_EN VINT PREREG VINTOK SHDN ENABLE LDO VINT 2A VINT OUT_LDO 0.925 x VREF EN VREG_ OK SS FB + + E/A + SSA VREF OVERLOAD MANAGEMENT OVERL LX 0.3V SGND CLK + CPWM + PFM SCLK PCLK PGND LOGIC DVREG REF_ILIM + PFM CLK REF_PFM BST HIGH-SIDE CURRENT SENSE + VREF RESET + CT DRAIN 185mV + VREF MUX SET_LOD UVLO_SW
MAX15015/MAX15016
PCLK
LEVEL SHIFT LDO_OUT
PASS ELEMENT
VINT
VINT ISS
UVLO_LDO TSD SHDN
VINT
REF
DELAY COMPARATOR
COMP
IN S/W SYNC EN OSC RAMP
Figure 1. MAX15015/MAX15016 Simplified Block Diagram
14 ______________________________________________________________________________________
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
IN_SW EN_SYS IN_LDO
IN_LDO
7.0V OR 4.1V VINT VREFOK VINTOK 4.1V UVLO_LDO VINT VREF + UVLO_SW TSD SHDN VINT VREF VREFOK THERMAL SHDN TSD VREFOK VINTOK VREG_EN VINT PREREG VINTOK SHDN ENABLE LDO UVLO_SW
MAX15014/MAX15017
PASS ELEMENT + VINT 2A VINT OUT_LDO 0.925 x VREF VREG_ OK EN + + VREF + 185mV VREF MUX
LDO_OUT
REG
REG_LDO
+
SET_LOD
VREG_OK EN_SW
VINT
VINT ISS
UVLO_LDO TSD SHDN
VINT
REF
RESET
DELAY COMPARATOR CT DRAIN REF_ILIM + PFM CLK REF_PFM BST HIGH-SIDE CURRENT SENSE
SS FB
+ E/A -
+ SSA -
ILIM VREF OVERLOAD MANAGEMENT
-
COMP OVERL
IN S/W SYNC EN OSC RAMP 0.3V SGND CLK + CPWM
LOGIC + PFM SCLK PCLK DVREG
LX
PGND
Figure 2. MAX15014/MAX15017 Simplified Block Diagram
Table 1. Enable Inputs Configuration
EN_SYS Low Low High High EN_SW Low High Low High LDO REGULATOR Off Off On On DC-DC SWITCHING CONVERTER Off Off Off On
The MAX15014-MAX15017 provide undervoltage lockout (UVLO). The UVLO monitors the input voltage (VIN_LDO) and is fixed at 4.1V (MAX15015/MAX15016) or 7V (MAX15014/MAX15017).
Internal Linear Regulator (REG)
REG is the output terminal of a 5V (MAX15015/ MAX15016), or 8V (MAX15014/MAX15017) LDO which is powered from IN_SW and provides power to the IC.
Connect REG externally to DVREG to provide power for the high-side MOSFET gate driver. Bypass REG to SGND with a ceramic capacitor (CREG) of at least 1F. Place the capacitor physically close to the MAX15014- MAX15017 to provide good bypassing. During normal operation, REG is intended for powering up only the internal circuitry and should not be used to supply power to external loads.
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15
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Soft-Start and Reference (SS)
SS is the 1.235V reference bypass connection for the MAX15014-MAX15017 and also controls the soft-start period. At startup, after input voltage is applied at IN_SW, IN_LDO and the UVLO thresholds are reached, the device enters soft-start. During soft-start, 14A is sourced into the capacitor (CSS) connected from SS to SGND causing the reference voltage to ramp up slowly. When VSS reaches 1.244V, the output becomes fully active. Set the soft-start time (tSS) using following equation: V x CSS t SS = SS ISS where VSS = soft-start reference voltage = 1.235V (typ), ISS = soft-start current = 14 x 10-6A (typ), tSS is in seconds and CSS is in Farads. 80dB open-loop gain and a 1.8MHz GBW product. See the Typical Operating Characteristics for the Gain and Phase vs. Frequency graph.
Oscillator/Synchronization Input (SYNC)
With SYNC connected to SGND, the MAX15014- MAX15017 use their internal oscillator and switch at a fixed frequency of 135kHz and 500kHz. The MAX15014/ MAX15016 are the 135kHz options and MAX15015/ MAX15017 are the 500kHz options. For external synchronization, drive SYNC with an external clock from 400kHz to 600kHz (MAX15015/MAX15017) or 100kHz to 200kHz (MAX15014/MAX15016). When driven with an external clock, the device synchronizes to the rising edge of SYNC.
PWM Comparator/Voltage Feed-Forward
An internal ramp generator clocked by the internal oscillator is compared against the output of the error amplifier to generate the PWM signal. The maximum amplitude of the ramp (VRAMP) automatically adjusts to compensate for input voltage and oscillator frequency changes. This causes the V IN_SW / V RAMP to be a constant 10V/V across the input voltage range of 4.5V to 40V (MAX15015/MAX15016) or 7.5V to 40V (MAX15014/ MAX15017) and the SYNC frequency range of 400kHz to 600kHz (MAX15015/MAX15017) or 100kHz to 200kHz (MAX15014/MAX15016).
Internal Charge Pump (MAX15015/MAX15016)
The MAX15015/MAX15016 feature an internal charge pump to enhance the turn-on of the internal MOSFET, allowing for operation with input voltages down to 4.5V. Connect a flying capacitor (CF) between C+ and C-, a boost diode from C+ to BST, as well as a bootstrap capacitor (CBST) between BST and LX to provide the gate drive voltage for the high-side n-channel DMOS switch. During the on-time, the flying capacitor is charged to VDVREG. During the off-time, the positive terminal of the flying capacitor (C+) is pumped to two times VDVREG and charge is dumped onto CBST to provide twice the regulator voltage across the high-side DMOS driver. Use a ceramic capacitor of at least 0.1F for CBST and CF located as close as possible to the device.
Output Short-Circuit Protection (Hiccup Mode)
The MAX15014-MAX15017 protect against an output short circuit by utilizing hiccup-mode protection. In hiccup mode, a series of sequential cycle-by-cycle current-limit events cause the part to shut down and restart with a soft-start sequence. This allows the device to operate with a continuous output short circuit. During normal operation, the current is monitored at the drain of the internal power MOSFET. When the current limit is exceeded, the internal power MOSFET turns off until the next on-cycle and a counter increments. If the counter counts seven consecutive current-limit events, the device discharges the soft-start capacitor and shuts down for 512 clock periods before restarting with a soft-start sequence. Each time the power MOSFET turns on and the device does not exceed the current limit, the counter is reset.
Gate Drive Supply (DVREG)
DVREG is the supply input for the internal high-side MOSFET driver. The power for DVREG is derived from the output of the internal regulator (REG). Connect DVREG to REG externally. To filter the switching noise, the use of an RC filter (1 and 0.47F) from REG to DVREG is recommended. In the MAX15015/MAX15016, the high-side drive supply is generated using the internal charge pump along with the bootstrap diode and capacitor. In the MAX15014/MAX15017, the high-side MOSFET driver supply is generated using only the bootstrap diode and capacitor.
Error Amplifier
The output of the internal error amplifier (COMP) is available for frequency compensation (see the Compensation Design section). The inverting input is FB, the noninverting input SS, and the output COMP. The error amplifier has an
LDO Regulator
The LDO regulator operates over an input voltage from 5V to 40V, and can be enabled independently of the DC-DC converter section. Its quiescent current is as low as 47A with a load current of 100A. All devices
16
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
feature a preset output voltage of 5V (MAX1501_A) or 3.3V (MAX1501_B). Alternatively, the output voltage can be adjusted using an external resistive-divider network connected between LDO_OUT, SET_LDO, and SGND. See Figure 5.
Inductor Selection
Three key inductor parameters must be specified for operation with the MAX15014-MAX15017: inductance value (L), peak inductor current (IPEAK), and inductor saturation current (ISAT). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current (IP-P). Higher IP-P allows for a lower inductor value while a lower IP-P requires a higher inductor value. A lower inductor value minimizes size and cost and improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. On the other hand, higher inductance increases efficiency by reducing the IP-P. Resistive losses due to extra wire turns can exceed the benefit gained from lower I P-P levels especially when the inductance is increased without also allowing for larger inductor dimensions. A good compromise is to choose IP-P equal to 40% of the full load current. Calculate the inductor using the following equation: (V - V ) V L = OUT IN OUT VIN x fSW x IP-P VIN and VOUT are typical values so that efficiency is optimum for typical conditions. The switching frequency (f SW ) is internally fixed at 135kHz (MAX15014/ MAX15016) or 500kHz (MAX15015/MAX15017) and can vary when synchronized to an external clock (see the Oscillator/Synchronization Input (SYNC) section). The IP-P, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. See the Output-Capacitor Selection section to verify that the worst-case output ripple is acceptable. The inductor current (ISAT) is also important to avoid current runaway during continuous output short circuit. Select an inductor with an I SAT specification higher than the maximum peak current limit of 2.6A.
MAX15014-MAX15017
RESET Output
The RESET output is typically connected to the reset input of a microprocessor (P). A P's reset input starts or restarts the P in a known state. The MAX15014- MAX15017 supervisory circuits provide the reset logic to prevent code-execution errors during power-up, power-down, and brownout conditions. RESET changes from high to low whenever the monitored voltage drops below the RESET threshold voltage. Once the monitored voltage exceeds its respective RESET threshold voltage(s), RESET remains low for the RESET timeout period, then goes high. The RESET timeout period is adjustable with an external capacitor (CCT) connected to CT.
Thermal-Shutdown Protection
The MAX15014-MAX15017 feature thermal shutdown protection which limits the total power dissipation in the device and protects it in the event of an extended thermal fault condition. When the die temperature exceeds +160C, an internal thermal sensor shuts down the part, turning off the DC-DC converter and the LDO regulator, and allowing the IC to cool. After the die temperature falls by 20C, the part restarts with a soft-start sequence.
Applications Information
Setting the Output Voltage
Connect a resistive divider (R3 and R4, see Figures 6 and 7) from OUT to FB to SGND to set the output voltage. Choose R3 and R4 so that DC errors due to the FB input bias current do not affect the output-voltage setting precision. For the most common output-voltage settings (3.3V or 5V), R3 values in the 10k range are adequate. Select R3 first and calculate R4 using the following equation: R4 = R3 VOUT - 1 VFB
Input-Capacitor Selection
The discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to keep the input voltage ripple within design requirements. The input voltage ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of VQ and VESR. Calculate the input capacitance and ESR required for a specified ripple using the following equations:
where VFB = 1.235V.
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17
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
ESR = VESR IP-P 2 IOUT _ MAX x D IOUT _ MAX + VQ x fSW tance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (t RESPONSE) depends on the closed-loop bandwidth of the converter (see the Compensation Design section). The resistive drop across the output capacitor's ESR, the drop across the capacitor's ESL (VESL), and the capacitor discharge causes a voltage droop during the loadstep. Use a combination of low-ESR tantalum/aluminum electrolytic and ceramic capacitors for better transient load and voltage ripple performance. Non-leaded capacitors and capacitors in parallel help reduce the ESL. Keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ESR = VESR ISTEP I xt COUT = STEP RESPONSE VQ VESL x t STEP ESL = ISTEP 1 tRESPONSE 3 C
CIN =
where CIN is the sum of CDRAIN and additional decoupling capacitance at the buck converter input, (V - V ) x VOUT IP-P = IN OUT and VIN x fSW x L V D = OUT VIN IOUT_MAX is the maximum output current, D is the duty cycle, and fSW is the switching frequency. The MAX15014-MAX15017 include UVLO hysteresis and soft-start to avoid chattering during turn-on. However, use additional bulk capacitance if the input source impedance is high. Use enough input capacitance at lower input voltages to avoid possible undershoot below the undervoltage lockout threshold during transient loading.
Output-Capacitor Selection
The allowable output voltage ripple and the maximum deviation of the output voltage during load steps determine the output capacitance (COUT) and its equivalent series resistance (ESR). The output ripple is mainly composed of VQ (caused by the capacitor discharge) and VESR (caused by the voltage drop across the ESR of the output capacitor). The equations for calculating the peak-to-peak output voltage ripple are: IP-P 8 x COUT x fSW VESR = ESR x IP-P VQ = Normally, a good approximation of the output voltage ripple is VRIPPLE = VESR + VQ. If using ceramic capacitors, assume the contribution to the output voltage ripple from ESR and the capacitor discharge to be equal to 20% and 80%, respectively. IP-P is the peak-to-peak inductor current (see the Input-Capacitor Selection section) and fSW is the converter's switching frequency. The allowable deviation of the output voltage during fast load transients also determines the output capaci-
where ISTEP is the load step, tSTEP is the rise time of the load step, tRESPONSE is the response time of the controller and fC is the closed-loop crossover frequency.
Compensation Design
The MAX15014-MAX15017 use a voltage-mode control scheme that regulates the output voltage by comparing the error amplifier output (COMP) with an internal ramp to produce the required duty cycle. The output lowpass LC filter creates a double pole at the resonant frequency, which has a gain drop of -40dB/decade. The error amplifier must compensate for this gain drop and phase shift to achieve a stable closed-loop system. The basic regulator loop consists of a power modulator, an output feedback divider, and a voltage error amplifier. The power modulator has a DC gain set by V IN / VRAMP, with a double pole and a single zero set by the output inductance (L), the output capacitance (COUT), and its ESR. The power modulator incorporates a voltage feed-forward feature, which automatically adjusts for variations in the input voltage resulting in a DC gain of 10.
18
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
The following equations define the power modulator: GMOD _ DC = fLC = VIN VRAMP 1 1 2 x x COUT x ESR = 10
C6 R6 R3 VOUT R4 REF EA COMP
MAX15014-MAX15017
C8
R5
C7
2 x x L x COUT
fZESR =
The switching frequency is internally set at 500kHz for MAX15015/MAX15017 and can vary from 400kHz to 600kHz when driven with an external SYNC signal. The switching frequency is internally set at 135kHz for MAX15014/MAX15016 and can vary from 100kHz to 200kHz when driven with an external sync signal. The crossover frequency (fC), which is the frequency when the closed-loop gain is equal to unity, should be set to around 1/10 of the switching frequency or below. The crossover frequency occurs above the LC doublepole frequency, and the error amplifier must provide a gain and phase bump to compensate for the rapid gain and phase loss from the LC double pole, which exhibits little damping. This is accomplished by utilizing a Type 3 compensator that introduces two zeroes and three poles into the control loop. The error amplifier has a low-frequency pole (fP1) near the origin so that tight voltage regulation at DC can be achieved. The two zeroes are at: fZI = and fZ2 = 1 2 x (R3 + R6) x C6 1 2 x R5 x C7
GAIN (dB)
CLOSED-LOOP GAIN EA GAIN
fZ1 fZ2
fC
fP2 fP3
FREQUENCY
Figure 3. Error Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Ceramic Capacitors
value and tend to be more expensive. Aluminum electrolytic capacitors have much larger ESR but can reach much larger capacitance values.
and the higher frequency poles are at: fP2 = and fP3 = 1 2 x R6 x C6
1 C7 x C8 2 x R5 x C7 + C8
Compensation when fC < fZESR This is usually the case when a ceramic capacitor is selected. In this case, fZESR occurs after fC. Figure 3 shows the error amplifier feedback as well as its gain response. fZ1 is set to 0.5 to 0.8 x fLC and fZ2 is set to fLC to compensate for the gain and phase loss due to the double pole. To achieve a 0dB crossover with -20dB/decade slope, poles fP2 and fP3 are set above the crossover frequency fC. The values for R3 and R4 are already determined in the Setting the Output Voltage section. The value of R3 is also used in the following calculations. Since fZ2 < fC < fP2, then R3 >> R6, and R3 + R6 can be approximated as R3. Now we can calculate C6 for zero fZ2 :
C6 = 1 2 x fLC x R3
The compensation design primarily depends on the type of output capacitor. Ceramic capacitors exhibit very low ESR, and are well suited for high-switchingfrequency applications, but are limited in capacitance
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19
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
fC occurs between fZ2 and fP2. In this region, the compensator gain (GEA) at fC is due primarily to C6 and R5. Therefore, GEA(fC) = 2 x fC x C6 x R5 and the modulator gain at fC is:
C6 R6 R3 VOUT R4 REF EA COMP C8 C7
R5
GMOD (fC ) =
GMOD _ DC (2 x fC )2 x L x COUT
Since GEA(fC) x GMOD(fC) = 1, R5 is calculated by: f x L x COUT x 2 R5 = C C6 x GMOD _ DC The frequency of fZ1 is set to 0.5 x fLC and now we can calculate C7: C7 = 1 0.5 x 2 x R5 x fLC
GAIN (dB)
CLOSED-LOOP GAIN
EA GAIN
fP2 is set at 1/2 the switching frequency (fSW). R6 is then calculated by: R6 = 1 2 x C6 x (0.5 x fSW )
fZ1 fZ2
fP2
fC
fP3
FREQUENCY
Figure 4. Error Amplifier Compensation Circuit (Closed-Loop and Error-Amplifier Gain Plot) for Higher ESR Output Capacitors
Note that if the crossover frequency has been chosen as 1/10 of the switching frequency, then fP2 = 5xfC. The purpose of fP3 is to further attenuate the residual switching ripple at the COMP pin. If the ESR zero (f ZESR) occurs in a region between fC and fSW / 2, then fP3 can be used to cancel it. This way, the Bode plot of the loop gain plot will not flatten out soon after the 0dB crossover, and will maintain its -20dB/decade slope up to 1/2 of the switching frequency. If the ESR zero well exceeds fSW/2 (or even fSW), fP3 should in any case be set high enough not to erode the phase margin at the crossover frequency. For example, it can be set between 5 x fC and 10 x fC. The value for C8 is calculated from: C8 = C7 (2 x C7 x R5 x fP3 - 1)
frequency is higher than fLC but lower than the closedloop crossover frequency. The equations that define the error amplifier's poles and zeros (fZ1, fZ2, fP2, and fP3) are the same as before. However, fP2 is now lower than the closed-loop crossover frequency. Figure 4 shows the error amplifier feedback as well as its gain response for circuits that use higher-ESR output capacitors (tantalum or aluminum electrolytic). Again, starting from R3, calculate C6 for zero fZ2: C6 = 1 2 x fLC x R3
and then place fP2 to cancel the ESR zero. R6 is calculated as: R6 = COUT x ESR C6
Compensation when fC > fZESR For larger ESR capacitors such as tantalum and aluminum electrolytic, fZESR can occur before fC. If fZESR < fC, then fC occurs between fP2 and fP3. fZ1 and fZ2 remain the same as before however, f P2 is now set equal to fZESR. The output capacitor's ESR zero
20
If the value obtained here for R6 is not considerably smaller than R3, then recalculate C6 using (R3 + R6) in place of R3. Then use the new value of C6 to obtain a better approximation for R6. The process can be further iterated, and convergence is ensured as long as fLC < fZESR.
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
The error amplifier gain between fP2 and fP3 is approximately equal to R5 / (R6 || R3). The ESR zero frequency fZESR might not be very much higher than the double-pole frequency fLC, therefore the value of R5 can be calculated as: R3 x R6 fC2 R5 = x R3 + R6 GMOD _ DC x fLC2 C7 can still be calculated as: C7 = 1 0.5 x 2 x R5 x fLC
MAX15014-MAX15017
VIN_LDO
IN_LDO LDO_OUT
MAX15014- MAX15017
SET_LDO
R1
R2 SGND
fP3 is set at 5xfC. Therefore, C8 is calculated as: C8 = C7 2 x C7 x R5 x fP3 - 1
Figure 5. Setting the Output Voltage Using a Resistive Divider
Setting the LDO Linear Regulator Output Voltage
The MAX15014-MAX15017 LDO regulator features Dual ModeTM operation: it can operate in either a preset voltage mode or an adjustable mode. In preset voltage mode, internal trimmed feedback resistors set the internal linear regulator to 3.3V or 5V (see the Selector Guide). Select preset voltage mode by connecting SET_LDO to ground. In adjustable mode, select an output voltage between 1.5V and 11V using two external resistors connected as a voltage-divider to SET_LDO (see Figure 5). Set the output voltage using the following equation: R1 VOUT = VSET _ LDO 1 + R2 where VSET_LDO = 1.241V and the recommended value for R2 is around 50k.
Connect CT to LDO_OUT to select the internally fixed timeout period. CCT must be low-leakage-type capacitor. Ceramic capacitors are recommended; do not use capacitors lower than 200pF to avoid the influence of parasitic capacitances.
Capacitor Selection and Regulator Stability
For stable operation over the full temperature range and with load currents up to 50mA, use a 10F (min) output capacitor (CLDO_OUT) with a maximum ESR of 0.4. To reduce noise and improve load-transient response, stability, and power-supply rejection, use larger output capacitor values. Some ceramic dielectrics such as Z5U and Y5V exhibit very large capacitance and ESR variation with temperature and are not recommended. With X7R or X5R dielectrics, 15F should be sufficient for operation over their rated temperature range. For higherESR tantalum capacitors (up to 1), use 22F or more to maintain stability. To improve power-supply rejection and transient response use a minimum 0.1F capacitor between IN_LDO and SGND.
Setting the RESET Timeout Delay
The RESET timeout period is adjustable to accommodate a variety of P applications. Adjust the RESET timeout period by connecting a capacitor (C CT ) between CT and SGND. t RP = CCT x VCT - TH ICT - THQ
Power Dissipation
The MAX15014-MAX15017 are available in a thermally enhanced package and can dissipate up to 2.86W at T A = +70C. When the die temperature reaches +160C, the part shuts down and is allowed to cool. After the die cools by 20C, the device restarts with a soft-start. The power dissipated in the device is the sum of the power dissipated in the LDO, power dissipated from supply current (PQ), transition losses due to switching the internal power MOSFET (PSW), and the
where VCT-TH = delay comparator threshold (rising) = 1.241V (typ), ICT-THQ = CT charge current = 2 x 10-6A (typ), tRP is in seconds and CCT is in Farads.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
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21
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
CIN_LDO R6 R3 VIN 4.5V TO 40V C8 C6 R5 C7 COMP FB VIN 5V TO 40V EN_SW EN_SYS C+ CF CSS SYNC PGND SGND REG CSS CREG 0.47F 1 DVREG PGND IN_LDO IN_SW
CIN_SW D1
CDRAIN
DRAIN BST CBST LX D2 L VOUT1 AT 1A COUT
R4
MAX15015 MAX15016
RESET CT LDO_OUT CCT SET_LDO SGND 10k VOUT2 AT 50mA
CLDO_OUT
Figure 6. MAX15015/MAX15016 Typical Application Circuit (4.5V to 40V Input Operation)
power dissipated due to the RMS current through the internal power MOSFET (PMOSFET). The total power dissipated in the package must be limited such that the junction temperature does not exceed its absolute maximum rating of +150C at maximum ambient temperature. Calculate the power lost in the MAX15014- MAX15017 using the following equations: The power loss through the switch: PMOSFET = (IRMS _ MOSFET )2 x RON IRMS _ MOSFET = D 2 x I PK + (IPK x IDC ) + I2 DC 3
RON is the on-resistance of the internal power MOSFET (see the Electrical Characteristics). The power loss due to switching the internal MOSFET: V xI x (t R + t F ) x fSW PSW = IN OUT 4 tR and tF are the rise and fall times of the internal power MOSFET measured at LX. The power loss due to the switching supply current (ISW): PQ = VIN _ SW x ISW The power loss due to the LDO regulator: PLDO = (VIN _ LDO - VLDO _ OUT ) x ILDO _ OUT The total power dissipated in the device will be: PTOTAL = PMOSFET + PSW + PQ + PLDO
I IPK = IOUT + P-P 2 IP-P IDC = IOUT - 2 VOUT D= VIN
22
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
CIN_LDO R6 R3 VIN 7.5V TO 40V C8 C6 R5 C7 COMP FB VIN 7.5V TO 40V EN_SW EN_SYS IN_LDO IN_SW
CIN_SW D1
CDRAIN
DRAIN BST CBST LX D2 L VOUT1 AT 1A COUT
R4
MAX15014 MAX15017
RESET SS SYNC PGND SGND REG CSS CREG 0.47F 1 DVREG PGND SET_LDO SGND CCT CLDO_OUT LDO_OUT CT 10k VOUT2 AT 50mA
Figure 7. MAX15014/MAX15017 Typical Application Circuit (7.5V to 40V Input-Voltage Operation)
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23
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Pin Configuration
31 COMP 29 SYNC 35 N.C. 30 N.C.
Chip Information
PROCESS: BiCMOS/DMOS
TOP VIEW
28 C+ (I.C.)
36 IN_SW
34 REG
33 SS
32 FB
N.C. N.C. N.C. RESET SGND CT EN_SW EN_SYS N.C.
1 2 3 4 5 6 7 8 9
+
27 26 25 24 23 22 21 20 19
N.C. N.C. DVREG N.C. C- (I.C.) PGND DRAIN DRAIN N.C.
MAX15014-MAX15017
EP*
10
11
12
13
14
15
16
17
SET_LDO
LDO_OUT
N.C.
IN_LDO
N.C.
BST N.C.
LX
( ) MAX15014/MAX15017 *EP = EXPOSED PAD.
TQFN
LX
18
Selector Guide
LDO OUTPUT PART MAX15014A MAX15014B MAX15015A MAX15015B MAX15016A MAX15016B MAX15017A MAX15017B SWITCHING FREQUENCY (kHz) 135 135 500 500 135 135 500 500 DC-DC MINIMUM INPUT VOLTAGE (V) 7.5 7.5 4.5 4.5 4.5 4.5 7.5 7.5 CHARGE PUMP -- -- X X X X -- -- 5V X -- X -- X -- X -- 3.3V -- X -- X -- X -- X ADJUSTABLE OUTPUT X X X X X X X X
24
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1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX15014-MAX15017
______________________________________________________________________________________
QFN THIN.EPS
25
1A, 4.5V to 40V Input Buck Converters with 50mA Auxiliary LDO Regulators MAX15014-MAX15017
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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